1. Field
This disclosure relates generally to clock circuits, and more specifically, to a square to pseudo-sinusoidal clock conversion circuit and method.
2. Related Art
In high speed data communication systems, there are many building blocks that require sinusoidal clock inputs to ensure analog performance of the block. For example, in quadrature mixing based phase interpolator circuit, it is very desirable to have sinusoidal clock inputs, as the sinusoidal clocks can have maximum clock edge overlap between in-phase clock (clock I) and quadrature-phase clock (clock Q) and proper phase interpolation can then be realized between input clock I phase and input clock Q phase. Another example, in analog multiplier based sinusoidal phase detector circuit, as widely used in frequency synthesizers, it is also very desirable to have sinusoidal clock inputs from a reference clock and from a feedback divider clock, as the multiplication between two sinusoidal clocks has much higher spectral purity and after being fed into a loop filter, lower phase noise or clock jitter can be realized at the frequency synthesizer final output. However, as CMOS (complementary metal oxide semiconductor) and CML (current mode logic) topology are widely used in high speed digital systems, which only output square-wave like clocks and are unsymmetrical in clock signal pull-up and pull-down, designing high performance analog blocks is usually avoided due to a lack of sinusoidal clocks. In addition, such analog blocks usually require a higher system level budget for the respective blocks. Furthermore, LC resonator circuits could be used for sinusoidal clock generation, however such circuits usually introduce process compatibility and large silicon area concerns due to a need for an on-die inductor device.
Accordingly, there is a need for an improved method and apparatus for overcoming the problems in the art as discussed above.